Two-step single-slope comparator with high linearity and CMOS image sensor including the same

ABSTRACT

A comparator includes a first comparison block suitable for sampling a pixel signal, comparing a sampled pixel signal with a coarse ramping voltage, outputting a first comparison signal, sampling a coarse step voltage and outputting a residue voltage as a difference voltage between the sampled pixel signal and a sampled coarse step voltage; and a second comparison block suitable for comparing a fine ramping voltage with the residue voltage of the first comparison block and outputting a second comparison signal.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority of Korean Patent Application No.10-2017-0105323, filed on Aug. 21, 2017, which is incorporated herein byreference in its entirety.

BACKGROUND 1. Field

Various embodiments of the present invention generally relate to acomplementary metal oxide semiconductor (CMOS) image sensor.Particularly, the embodiments relate to a two-step single-slopecomparator and a CMOS image sensor including the same for preventing alinearity error caused by an operation structure.

2. Description of the Related Art

A CMOS image sensor has a trade-off relationship between speed andpower. A CMOS image sensor with a column-parallel structure having anoptimum speed/power trade-off relationship is widely used.

An analog-to-digital converter (ADC) included in the CMOS image sensorhaving the column-parallel structure is typically integrated within ashallow width of a pixel, in which case a single-slope ADC is widelyused.

Recently, high resolution and high-speed operations of the CMOS imagesensor are required to meet the needs of customers and to meet therequirements of the various and increasing number of applications forsuch sensors.

However, it is technically difficult to implement a high-speed operationof the CMOS image sensor due to the operation speed limitations inproportion to the increase of the resolution according tocharacteristics of a single-slope ADC.

Thus, a two-step analog-to-digital converting device has been developedto implement the high-speed operation instead of the single-slope ADC.

The two-step analog-to-digital converting device performs ananalog-to-digital conversion operation by determining a most significantbit (MSB) value of a sampling value in a coarse step and a leastsignificant bit (LSB) value of the sampling value in a fine step. Thus,a two-step analog-to-digital converting device may improve operationspeed as compared with the single-step ADC.

Use of a two-step analog-to-digital converting device is shown in thefollowing documents: Alexey Yakovlev, “DOUBLE-RAMP ADC FOR CMOSSENSORS”; U.S. Pat. No. 6,670,904 B1; and Seunghyun Lim, “A High-SpeedCMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs,” IEEETrans. Electron Devices, vol. 56, no. 3, pp. 393-398, March. 2009.

In these documents, a coarse ramping voltage for MSB conversion isstored on a top plate of a capacitor and then, a voltage of a floatingstate stored in the top plate of the capacitor is changed according to afine ramping voltage when an input terminal for a fine ramping operationis coupled to a bottom plate of the capacitor during the fine rampingoperation for a LSB conversion.

That is, in these documents, the coarse ramping voltage and the fineramping voltage are alternating-current (AC) coupled in the top plate ofthe capacitor by sampling the coarse ramping voltage of a ramp signalgeneration device at the top plate of the capacitor and applying thefine ramping voltage to the bottom plate of the capacitor.

However, in these documents, when the fine ramping voltage is applied tothe bottom plate, a gain error occurs due to a parasitic capacitorbetween a gate and a source of an input transistor of a comparator, anda linearity error occurs between the MSB value and the LSB value.

In another application, a 4-input comparator using four inputtransistors is used for the two-step single-slope analog-to-digitalconversion.

However, in this other application, since a transfer conductance of eachinput transistor is changed according to a common voltage level, alinearity error is caused by a changed transfer conductance when thecommon voltage level is changed.

SUMMARY

Various embodiments are directed to a two-step single-slope comparatorand a CMOS image sensor including the same that uses as a residue valuea difference between a sampling value of a pixel signal and a samplingvalue of a first coarse step voltage and analog-to-digital-converts theresidue value.

In an embodiment, a comparator may include a first comparison blocksuitable for sampling a pixel signal, comparing a voltage of a sampledpixel signal to a coarse ramping voltage, outputting a first comparisonresult signal, sampling a coarse step voltage and outputting a residuevoltage, representing a difference between the voltage of the sampledpixel signal and the sampled coarse step voltage; and a secondcomparison block suitable for comparing a fine ramping voltage to theresidue voltage outputted by the first comparison block and outputting asecond comparison result signal.

In an embodiment, a complementary metal oxide semiconductor (CMOS) imagesensor may include a pixel array suitable for outputting a pixel signalcorresponding to an incident light; a row decoder suitable for selectingand controlling pixels of the pixel array row by row according to acontrol signal of a controller; a ramp signal generator suitable forgenerating a coarse ramping signal and a fine ramping signal accordingto the control signal of the controller; a first comparison blocksuitable for sampling the pixel signal outputted from the pixel array,comparing a sampled pixel signal to the coarse ramping signal outputtedby the ramp signal generator, outputting a first comparison resultsignal, sampling a coarse step voltage and outputting a residue voltage,representing a difference between a voltage of the sampled pixel signaland the sampled coarse step voltage; and a second comparison blocksuitable for comparing the fine ramping voltage outputted from the rampsignal generator to the residue voltage outputted by the firstcomparison block and outputting a second comparison result signal; acounter suitable for counting a clock of the controller according to thefirst comparison result signal outputted by the first comparison blockand the second comparison result signal outputted by the secondcomparison block; a memory suitable for storing counting information ofthe counter according to the control signal of the controller; a columnread-out circuit suitable for outputting data stored in the memoryaccording to the control signal of the controller; and the controllersuitable for controlling operations of the row decoder, the ramp signalgenerator, the first comparison block, the second comparison block, thecounter, the memory, and the column read-out circuit.

In an embodiment, a pixel array suitable for generating a pixel signal;a ramp signal generator suitable for generating coarse and fine rampingsignals; a first comparison block suitable for generating a firstcomparison result signal by comparing the pixel signal to the coarseramping signal; a second comparison block suitable for generating asecond comparison result signal by comparing the fine ramping signal toa difference between the pixel signal and a coarse step signal; acounter suitable for counting a clock according to the first and secondcomparison result signals; and a column read-out circuit suitable foroutputting a count result of the counter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a typical CMOS image sensor inaccordance with one or more embodiments of the present disclosure.

FIG. 2A is an exemplary circuit diagram illustrating a comparator shownin FIG. 1.

FIG. 2B is an exemplary timing diagram illustrating a rowanalog-to-digital conversion operation of the comparator shown in FIG.2A.

FIG. 2C is an exemplary digital double sampling (DDS) timing diagramillustrating a row analog-to-digital conversion operation of thecomparator shown in FIG. 2A.

FIG. 3A is another exemplary circuit diagram illustrating a comparatorshown in FIG. 1.

FIG. 3B is an exemplary timing diagram illustrating a horizontal periodof the comparator shown in FIG. 3A.

FIG. 4A is an exemplary circuit diagram illustrating a comparator inaccordance with an embodiment of the present invention.

FIG. 4B is an exemplary digital double sampling (DDS) timing diagramillustrating a row analog-to-digital conversion operation of thecomparator shown in FIG. 4A.

FIG. 4C is an exemplary diagram illustrating a crossing timing of thecomparator shown in FIG. 4A.

FIG. 5 is another exemplary circuit diagram illustrating a comparator inaccordance with another embodiment of the present invention.

FIG. 6 is a diagram illustrating a CMOS image sensor including acomparator in accordance with one or more embodiments of the presentinvention.

DETAILED DESCRIPTION

Various embodiments are described below with reference to theaccompanying drawings. However, as will be apparent to those skilled inthe art in light of the present disclosure, elements and features may beconfigured and arranged differently than shown in the disclosedembodiments. Thus, the disclosed embodiments are not to be construed aslimiting. Moreover, in the description below, reference to “anembodiment” does not necessarily mean only one embodiment, and differentreferences to “an embodiment” are not necessarily to the sameembodiment(s).

The drawings are not necessarily to scale and, in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the presentinvention.

As used herein, singular forms may include the plural forms as well,unless the context clearly indicates otherwise.

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Thepresent invention may be practiced without some or all of these specificdetails. In other instances, well-known process structures and/orprocesses have not been described in detail in order not tounnecessarily obscure the present invention.

Hereinafter, the various embodiments of the present invention will bedescribed in detail with reference to the attached drawings.

FIG. 1 is a diagram illustrating a typical CMOS image sensor inaccordance with an embodiment of the present disclosure. The typicalCMOS image sensor shown in FIG. 1 includes a column parallel structureusing a single-slope analog-to-digital conversion device.

Referring to FIG. 1, the typical CMOS image sensor includes a pixelarray 10, a row decoder 20, a ramp signal generator 30, a comparatorassembly 40, a counter assembly 50, a memory assembly 60, a columnread-out circuit 70, and a controller 80.

The pixel array 10 outputs a pixel signal corresponding to an incidentlight.

The row decoder 20 selects and controls pixels of the pixel array row byrow.

The ramp signal generator 30 generates a ramp signal V_(RAMP) (includinga coarse ramping signal and a fine ramping signal) in response to acontrol signal of the controller.

The comparator assembly 40 compares the ramp signal V_(RAMP) of the rampsignal generator 40 with each pixel signal outputted from the pixelarray.

The counter assembly 50 counts a clock of the controller 80 according toan output signal of the comparator assembly 40.

The memory assembly 60 stores counting information of the counterassembly 50 according to the control of the controller 80.

The column read-out circuit 70 outputs sequentially the stored data ofthe memory assembly 60 as a pixel data PXDATA according to the controlof the controller 80.

The controller 80 controls operations of the row decoder 20, the rampsignal generator 30, the comparator assembly 40, the counter assembly50, the memory assembly 60, and the column read-out circuit 70.

In general, in a CMOS image sensor, a correlated double sampling (CDS)technique for removing an offset value of the pixel is performed in thecomparator assembly 40.

The comparator assembly 40 includes a plurality of comparators 41, thecounter assembly 50 includes a plurality of counters 51, and the memoryassembly 60 includes a plurality of memories 61. That is, the comparator41, the counter 51 and the memory 61 are included in each column.

The operations of the comparator 41, the counter 51 and the memory 61will be described with reference to FIG. 1 below.

The comparator 41 receives a pixel signal outputted from a first columnof the pixel array 10 through a first terminal and receives a rampsignal V_(RAMP) outputted from the ramp signal generator 30. Thecomparator 41 compares the ramp signal V_(RAMP) with the pixel signaland outputs a comparison result signal according to the control of thecontroller 80.

Since a voltage level of the ramp signal V_(RAMP) increases or decreasesin an elapsed time after an initialization, a value of the ramp signalV_(RAMP) crosses a value of the pixel signal at a particular time. Avalue of the comparison result signal outputted from the comparator 41is inverted after the value of the ramp signal V_(RAMP) crosses thevalue of the pixel signal.

Thus, the counter 51 outputs the counting information by counting aclock of the controller 80 from a falling time of the ramp signal by theinversion time of the comparison result signal outputted from thecomparator 41. The counter 51 is initialized by a reset control signalof the controller 80.

The memory 61 stores and outputs the counting information of the counter51 to the column read-out circuit 70 according to the control signal ofthe controller 80.

The CMOS image sensor performs a counting operation on a reset signal(or a reset voltage) and then performs a counting operation on an imagesignal (a signal voltage).

FIG. 2A is an exemplary circuit diagram illustrating a comparator 41shown in FIG. 1.

FIG. 2B is a timing diagram illustrating a row analog-to-digitalconversion operation of the comparator 41 shown in FIG. 2A.

FIG. 2C is a digital double sampling (DDS) timing diagram illustrating arow analog-to-digital conversion operation of the comparator 41 shown inFIG. 2A.

Referring to FIG. 2A, the comparator 41 includes a first comparisonblock 210 and a second comparison block 220.

The first comparison block 210 samples a pixel signal V_(PIXEL),compares a sampled pixel signal with a coarse ramping signal, andoutputs a first comparison result signal. The first comparison block 210samples a coarse step voltage V_(MSB), changes a sampled coarse stepvoltage to a fine ramping voltage, compares the pixel signal with thefine ramping voltage, and outputs a second comparison result signal.

The second comparison block 220 amplifies the first comparison resultsignal and the second comparison result signal outputted from the firstcomparison block 210, and outputs amplified first and second comparisonresult signals to the counter 51.

Structurally, the first comparison block 210 includes a first capacitorC₁₁, a first switch SW_(R11), a second switch SW_(MSB1), a secondcapacitor C₁₂, a third switch SW_(S/H1), a fourth switch SW_(LSB1), anda first comparator FIRST COMPARATOR.

The first capacitor C₁₁ samples the pixel signal V_(PIXEL) receivedthrough a first terminal thereof, and a second terminal of the firstcapacitor C₁₁ is coupled to a negative input node of the firstcomparator FIRST COMPARATOR.

The first switch SW_(R11) is coupled to form a first feedback loopbetween the negative input node of the first comparator FIRST COMPARATORand an output node of the first comparator FIRST COMPARATOR.

The second switch SW_(MSB1) switches on or off a coarse ramping voltagereceived through a first terminal thereof, and a second terminal of thesecond switch SW_(MSB1) is coupled to a positive input node of the firstcomparator FIRST COMPARATOR.

The second capacitor C₁₂ samples a coarse step voltage V_(MSB), and afirst terminal of the second capacitor C₁₂ is coupled to positive inputnode of the first comparator FIRST COMPARATOR.

The third switch SW_(S/H1) is coupled between a second terminal of thesecond capacitor C₁₂ and a ground terminal, for example, having a firstground voltage V_(GND1) for a MSB conversion or a second ground voltageV_(GND2) for a LSB conversion.

The fourth switch SW_(LSB1) switches on or off the fine ramping voltagereceived through a first terminal of the fourth switch SW_(LSB1) and asecond terminal of the fourth switch SW_(LSB1) is coupled to the secondterminal of the second capacitor C₁₂.

The first comparator FIRST COMPARATOR compares the pixel signalV_(PIXEL) sampled at the first capacitor C₁₁ to the coarse rampingvoltage, and outputs a first comparison result signal. The firstcomparator FIRST COMPARATOR compares the coarse step voltage V_(MSB),which is sampled at the second capacitor C₁₂ and is changed according tothe fine ramping voltage, to the pixel signal V_(PIXEL), and outputs asecond comparison result signal.

The second comparison block 220 includes third capacitor C₁₃, fifthswitch SW_(R12) and a second comparator SECOND COMPARATOR.

The third capacitor C₁₃ is coupled between the first comparison block210 and a negative input node of the second comparator SECOND COMPARATORand cuts off the transfer of a direct current (DC).

The fifth switch SW_(R12) is coupled to form a second feedback loopbetween the negative input node of the second comparator SECONDCOMPARATOR and an output node of the second comparator SECONDCOMPARATOR.

A positive input node of the second comparator SECOND COMPARATOR iscoupled to a ground terminal having a first ground voltage V_(GND1) or asecond ground voltage V_(GND2). The first ground voltage V_(GND1) is acircuit ground voltage V_(Circuit) _(_) _(GND) and the second groundvoltage V_(GND2) is a voltage V_(Circuit) _(_) _(GND)−V_(offset)acquired by subtracting an offset voltage V_(offset) from the circuitground voltage V_(Circuit) _(_) _(GND).

The second comparator SECOND COMPARATOR amplifies the first comparisonresult signal and the second comparison result signal of the firstcomparison block 210, and outputs the amplified first and secondcomparison result signals to the counter 51.

Each switch shown in FIG. 2A may be switched on or off according to thecontrol signal of the controller 80.

Operation of the CDS technique will be described with reference to FIGS.2A and 2B below.

If a reset voltage V_(RST) of the pixel signal V_(PIXEL) is applied, andthe first switch SW_(R11), the second switch SW_(MSB1), the third switchSW_(S/H1) and the fifth switch SW_(R12) are switched on, the firstfeedback loop is formed on the first comparator FIRST COMPARATOR throughthe first switch SW_(R11) and the second feedback loop is formed on thesecond comparator thorough the fifth switch SW_(R12). Thus, the resetvoltage V_(RST) of the pixel signal V_(PIXEL) is sampled at the firstcapacitor C₁₁, and the output voltage V_(OUT1) of the first comparatorFIRST COMPARATOR and the negative input voltage V_(IN13) of the secondcomparator SECOND COMPARATOR become a common voltage through the thirdcapacitor C₁₃.

Subsequently, if the first switch SW_(R11) and the fifth switch SW_(R12)are switched off, and the signal voltage V_(SIG) of the pixel signalV_(PIXEL) is applied, a signal voltage V_(SIG)-reset voltage V_(RST) isinputted to the negative input node of the first comparator FIRSTCOMPARATOR through the first capacitor C₁₁, and a change value (i.e.,difference between the signal voltage V_(SIG) and the reset voltageV_(RST)) of the pixel signal V_(PIXEL) is sampled.

If the coarse ramping voltage of the ramp signal V_(RAMP) is applied tothe positive input node of the first comparator FIRST COMPARATOR and isramped with a coarse step, the first comparator FIRST COMPARATORcompares the negative input node voltage V_(IN11) to the positive inputnode voltage V_(IN12) and outputs a comparison result signal when thenegative input node voltage V_(IN11) becomes greater than the positiveinput node voltage V_(IN12) (that is, from V_(IN1)−V_(IN12)<0 toV_(IN1)−V_(IN12)>0). Thus, the first comparator FIRST COMPARATORaccomplishes the MSB conversion, and the second switch SW_(MSB1) and thethird switch SW_(S/H1) are switched off.

The coarse step voltage V_(MSB) is sampled at the second capacitor C₁₂.

As described above, after the MSB conversion is completed through thecoarse step, if the fourth switch SW_(LSB1) is switched on, the fineramping voltage of the ramp signal V_(RAMP) is applied to the positiveinput node of the first comparator through the second capacitor C₁₂, andthe ramping operation starts through the fine step and changes thecoarse voltage. Thus, the LSB conversion is completed.

The positive input node voltage V_(IN12) has a sum value of the coarsestep voltage V_(MSB) and the fine step voltage V_(LSB) due to thecharges sampled at the second capacitor C₁₂ during the MSB conversionoperation.

An operation of a digital double sampling (DDS) operation will bedescribed with reference to FIGS. 2A and 2C.

If the reset voltage V_(RST) of the pixel signal V_(PIXEL) is applied,and the first switch SW_(R11), the second switch SW_(MSB1), the thirdswitch SW_(S/H1) and the fifth switch SW_(R12) are switched on, thefirst feedback loop is formed to the first comparator through the firstswitch SW_(R11) and the second feedback loop is formed on the secondcomparator SECOND COMPARATOR thorough the fifth switch SW_(R12). Thus,the reset voltage V_(RST) of the pixel signal V_(PIXEL) is sampled atthe first capacitor C₁₁, the output voltage V_(OUT1) of the firstcomparator FIRST COMPARATOR and the negative input voltage V_(IN13) ofthe second comparator SECOND COMPARATOR become a common voltage throughthe third capacitor C₁₃.

Subsequently, if the first switch SW_(R11) and the fifth switch SW_(R12)are switched off, and the coarse ramping voltage of the ramp signalV_(RAMP) is applied to the positive input node of the first comparatorFIRST COMPARATOR and is ramped with the coarse step, the firstcomparator FIRST COMPARATOR compares the negative input node voltageV_(IN11) to the positive input node voltage V_(IN12) and outputs acomparison result signal when the negative input node voltage V_(IN11)becomes greater than the positive input node voltage V_(IN12) (that is,from V_(IN1)−V_(IN12)<0 to V_(IN1)−V_(IN12)>0). Thus, the firstcomparator FIRST COMPARATOR accomplishes the MSB conversion, a codevalue is stored, and the second switch SW_(MSB1) and the third switchSW_(S/H1) are switched off.

The coarse step voltage V_(MSB) is sampled at the second capacitor C₁₂.

As described above, after the MSB conversion is completed through thecoarse step, if the fourth switch SW_(LSB1) is switched on, the fineramping voltage of the ramp signal V_(RAMP) is applied to the positiveinput node of the first comparator FIRST COMPARATOR through the secondcapacitor C₁₂, and the ramping operation starts through the fine step.Thus, the LSB conversion is completed and the code value is stored.

Subsequently, if the signal voltage V_(SIG) of the pixel signalV_(PIXEL) is applied, after a code value is stored by performing theabove-described two-step operations (the coarse step and the fine step),the DDS operation may be implemented by subtracting the code value ofthe reset voltage V_(RST) from the code value of the signal voltageV_(SIG).

However, the comparator shown in FIG. 2A has a gain error due to aparasitic capacitor between the second capacitor C₁₂ and a gate and asource of the input transistor of the first comparator FIRST COMPARATORwhen the fine ramp voltage of the ramp signal V_(RAMP) is appliedthrough the second capacitor C₁₂.

Thus, a voltage value of (coarse step voltage+fine step voltage)×gainerror is applied to the positive input node of the first comparatorFIRST COMPARATOR, and the non-linearity is increased.

FIG. 3A is another exemplary circuit diagram illustrating a comparator41 shown in FIG. 1.

FIG. 3B is a timing diagram illustrating a horizontal period of thecomparator 41 shown in FIG. 3A.

Referring to FIG. 3A, the comparator 41 according to another embodimentof the present invention includes a pre-amplifier 310, a signalprocessor 320, a coarse ramping voltage sampling circuit 330, and acommon mode voltage sampling circuit 360.

The common mode voltage sampling circuit 360 samples a common modevoltage V_(CM) according to a sampling control signal of the signalprocessor 320.

The coarse ramping voltage sampling circuit 330 samples a coarse rampingvoltage V_(RAMP) _(_) _(C) according to a sampling control signal of thesignal processor 320.

The pre-amplifier 310 amplifies a difference between an input voltageV_(p) and a sampled coarse ramping voltage V_(SP) and outputs a coarseconversion result. The pre-amplifier 310 amplifies a difference betweena fine ramping voltage V_(RAMP) _(_) _(F) and a sampled common modevoltage V_(SN) of the common mode voltage sampling circuit 360 andoutputs a fine conversion result.

The signal processor 320 generates the sampling control signal accordingto the coarse conversion result of the pre-amplifier 310, and outputs acomparison result signal to the counter 51 or a line memory 61 accordingto the coarse conversion result and the fine conversion result of thepre-amplifier 310.

More specifically, the common mode voltage sampling circuit 360 includesa first switch 361 and a first capacitor 362.

The first switch 361 cuts off the common mode voltage V_(CM) accordingto the sampling control signal of the signal processor 320.

The first capacitor 362 stores the common mode voltage V_(CM) at acutting-off time of the first switch 361.

The coarse ramping voltage sampling circuit 330 includes a second switch331 and a second capacitor 332.

The second switch 331 cuts off the coarse ramping voltage V_(RAMP) _(_)_(C) according to the sampling control signal of the signal processor320.

The second capacitor 332 stores the coarse ramping voltage V_(RAMP) _(_)_(C) at a cutting-off time of the second switch 331.

The signal processor 320 includes an amplifier 321, a controller 322 andselector 323.

The amplifier 321 amplifies the coarse conversion result and the fineconversion result of the pre-amplifier 310.

The controller 322 generates the sampling control signal according tothe coarse conversion result of the amplifier 321.

The selector 323 selects the coarse conversion result of the amplifiervia the controller 322 or the fine conversion result of the amplifier321 according to a selection signal SEL_(F) received from a timinggenerator (not shown), for example. The selector 323 outputs thecomparison result signal to the counter 51 or the line memory 61.

The coarse conversion result is synchronized with sampling clocks CLKsof the controller 322 and is transferred to the selector 323.

The amplifier 321 may be an additional element. That is, the signalprocessor 320 may be implemented without the amplifier 321. In thiscase, the coarse conversion result of the pre-amplifier 310 istransferred to the controller 322 and the fine conversion result of thepre-amplifier 310 is transferred to the selector 323.

The comparator 41 may further include a third switch 340 for resettingthe pre-amplifier 310 according to the control signal. That third switch340 resets the pre-amplifier 310 by switching on or off an outputvoltage of the pre-amplifier 310, which is feedback to an input terminalof the pre-amplifier 310, according to a control signal from anothercontroller (not shown).

Also, the comparator 41 may further include a third capacitor 350 fordecoupling the pixel voltage V_(PIXEL) from the output voltage of thepre-amplifier 310, which is feedback.

Operation of the comparator shown in FIG. 3A will be described withreference to FIG. 3B.

At a first step, the input voltage V_(p) of the pre-amplifier 310 iscompared to the sampled coarse ramping voltage V_(sp) of the coarseramping voltage sampling circuit 330. The difference between the inputvoltage V_(p) of the pre-amplifier 3210 and the sampled coarse rampingvoltage V_(sp) of the coarse ramping voltage sampling circuit 330 isamplified and transferred as an output voltage V_(OUT1) of thepre-amplifier 310 to the signal processor 320 via the output terminal ofthe pre-amplifier 310.

The output voltage V_(OUT1) of the pre-amplifier 310 enables the signalprocessor 320 to generate the sampling control signal. The second switch331 is switched off in response to the sampling control signal, and thecoarse ramping voltage V_(RAMP) _(_) _(C), which is passing through thesecond switch 331, is stored on the second capacitor 332. At the sametime, the signal processor 320 transfers the comparison result signal tothe counter 51 such that a coarse digital code is determined.

At a second step, the pre-amplifier 310 amplifies the difference betweenthe fine ramping voltage V_(RAMP) _(_) _(F) of the pre-amplifier 310 andthe sampled common mode voltage V_(SN) of the common mode voltagesampling circuit 360, and outputs the fine conversion result. The outputvoltage V_(OUT1) of the pre-amplifier 310 is transferred to the signalprocessor 320 via the output terminal of the pre-amplifier 310. Then,the signal processor 320 transfers the comparison result signal to thecounter 51 such that a fine digital code is determined.

However, in the comparator shown in FIG. 3A, a linearity error caused bya transfer conductance of each input transistor occurs because thetransfer conductance of the each input transistor is changed accordingto the common voltage level.

Thus, in embodiments of the present invention, in order to prevent thelinearity error caused by a conventional two-step single-slopeanalog-to-digital conversion structure, an analog-to-digital-convertingoperation is performed on a residual value, which is a differencebetween a sampling value of a pixel signal and a sampling value ofcoarse step voltage.

Hereinafter, a comparator according to embodiments of the presentinvention will be described with reference to FIGS. 4A to 6.

FIG. 4A is an exemplary circuit diagram illustrating a comparator 42 inaccordance with an embodiment of the present invention.

FIG. 4B is a digital double sampling (DDS) timing diagram illustrating arow analog-to-digital conversion operation of the comparator 42 shown inFIG. 4A.

FIG. 4C is a diagram illustrating a crossing timing of the comparator 42shown in FIG. 4A.

Referring to FIG. 4A, a comparator 42 in accordance with an embodimentof the present invention includes a first comparison block 410 and asecond comparison block 420.

The first comparison block 410 samples a pixel signal V_(PIXEL),compares a sampled pixel signal V_(PIXEL) with a coarse ramping voltage,and outputs a first comparison result signal. The first comparison block410 samples a coarse step voltage V_(MSB), and outputs a residue voltageV_(RES), which represents a difference between the sampled pixel signaland the sampled coarse step voltage.

The second comparison block 420 compares a fine ramping voltage with theresidue voltage V_(RES) of the first comparison block 410, and outputs asecond comparison result signal.

Structurally, the first comparison block 410 includes a first capacitorC₂₁, a first switch SW_(R21), a second switch SW_(S/H2), a secondcapacitor C₂₂, a third switch SW_(MSB2), a fourth switch SW_(RES) and afirst comparator FIRST COMPARATOR.

The first capacitor C₂₁ samples a pixel signal V_(PIXEL) receivedthrough a first terminal thereof, and a second terminal of the firstcapacitor C₂₁ is coupled to a positive input node of the firstcomparator FIRST COMPARATOR.

The first switch SW_(R21) is coupled between the positive input node anda negative input node of the first comparator FIRST COMPARATOR.

The second switch SW_(S/H2) switches on or off a coarse ramping voltageof the ramp signal V_(RAMP) received through a first terminal thereof,and a second terminal of the second switch SW_(S/H2) is coupled to thenegative input node of the first comparator FIRST COMPARATOR.

The second capacitor C₂₂ samples a coarse step voltage V_(MSB) and afirst terminal of the second capacitor C₂₂ is coupled to the secondterminal of the second switch SW_(S/H2) and the negative input node ofthe first comparator FIRST COMPARATOR.

The third switch SW_(MSB2) is coupled between the second terminal of thesecond capacitor C₂₂ and a ground terminal, for example, a circuitground terminal V_(Circuit) _(_) _(GND).

The fourth switch SW_(RES) is coupled to form the first feedback loopbetween the second terminal of the second capacitor C₂₂ and an outputnode of the first comparator FIRST COMPARATOR.

The first comparator FIRST COMPARATOR compares a sampled pixel signal ofthe first capacitor C₂₁ to the coarse ramping voltage applied throughthe second switch SW_(S/H2), and outputs a first comparison resultsignal. The first comparator FIRST COMPARATOR outputs a residue voltageV_(RES), which represents the difference between the sampled pixelsignal of the first capacitor C₂₁ and the sampled coarse step voltage ofthe second capacitor C₂₂.

The second comparison block 420 includes a third capacitor C₂₃, a fifthswitch SW_(R22), a sixth switch SW_(LSB2b), a seventh switch SW_(LSB2)and a second comparator SECOND COMPARATOR.

The third capacitor C₂₃ transfers the residue voltage V_(RES) outputtedfrom the first comparison block 410 to a negative input node of thesecond comparator SECOND COMPARATOR.

The fifth switch SW_(R22) is coupled to form a second feedback loopbetween the negative input node of the second comparator SECONDCOMPARATOR and an output node of the second comparator SECONDCOMPARATOR.

The sixth switch SW_(LSB2b) is coupled between a positive input node ofthe second comparator SECOND COMPARATOR and a ground terminal, forexample, having a voltage V_(Circuit) _(_) _(GND)−V_(offset) acquired bysubtracting an offset voltage V_(offset) from the circuit ground voltageV_(Circuit) _(_) _(GND).

The seventh switch SW_(LSB2) switches on or off the fine ramping voltagereceived through a first terminal thereof, and a second terminal of theseventh switch SW_(LSB2) is coupled to the positive input node of thesecond comparator SECOND COMPARATOR.

The second comparator SECOND COMPARATOR compares the residue voltageV_(RES) transferred from the first comparison block 410 through thethird capacitor C₂₃ to the fine ramping voltage applied through theseventh switch SW_(LSB2), and outputs a second comparison result signal.

Each switch shown in FIG. 4A may be switched on or off according to acontrol signal of a controller (not shown), which may be, for example, atiming generator, or according to a feedback control signal of thecomparator 42.

Next, operation of digital double sampling (DDS) will be described withreference to FIGS. 4B and 4C.

First, if the first switch SW_(R21), the second switch SW_(S/H2), thethird switch SW_(MSB2), the fifth switch SW_(R22) and the sixth switchSW_(LSB2b) are switched on, the coarse ramping voltage of the rampsignal V_(RAMP) is applied through second switch SW_(S/H2), the positiveinput node and the negative input node of the first comparator FIRSTCOMPARATOR are coupled through the first switch SW_(R21), the secondfeedback loop is formed to the second comparator SECOND COMPARATORthrough the fifth switch SW_(R22), the second capacitor C₂₂ is coupledto the first ground terminal having a circuit ground voltage V_(Circuit)_(_) _(GND) through the third switch SW_(MSB2), and the positive inputnode of the second comparator SECOND COMPARATOR is coupled to the secondground terminal, which has the voltage V_(Circuit) _(_)_(GND)−V_(offset) acquired by subtracting the offset voltage V_(offset)from the circuit ground voltage V_(Circuit) _(_) _(GND). Thus, thevoltage values of all nodes are initialized.

If a reset voltage V_(RST) of the pixel signal V_(PIXEL) is applied, thereset voltage V_(RST) is sampled at the first capacitor C₂₁, and thesampled reset voltage is applied to the positive input node of the firstcomparator FIRST COMPARATOR with a positive input voltage V_(IN21).

Subsequently, the first switch SW_(R21) and the fifth switch SW_(R22)are switched off, and the coarse ramping voltage of the ramp signalV_(RAMP) is applied to the negative input node of the first comparatorFIRST COMPARATOR with a negative input voltage V_(IN22) and is rampedwith the coarse step.

Thus, the first comparator FIRST COMPARATOR compares the positive inputvoltage V_(IN21) to the negative input voltage V_(IN22) and outputs afirst comparison result signal when the reset voltage V_(RST) is changedto be less than the coarse ramping voltage (that is, changed from resetvoltage-coarse voltage >0 to reset voltage-coarse ramping voltage <0, asindicated by reference numeral 430 of FIG. 4C). The output voltageV_(OUT1) of the first comparator FIRST COMPARATOR and the output voltageV_(OUT2) of the second comparator SECOND COMPARATOR are latched, and thecounted code value is stored as an MSB conversion code value on aregister.

The third switch SW_(MSB2) and the second switch SW_(S/H2) aresequentially switched off, and the coarse step voltage V_(MSB) issampled at the second capacitor C₂₂.

Subsequently, the fourth switch SW_(RES) is switched on, and the firstfeedback loop of the first comparator FIRST COMPARATOR is formed throughthe second capacitor C₂₂. The difference voltage of the reset voltageV_(RST) and the coarse step voltage V_(MSB) is outputted as a residuevoltage through the output node of the first comparator FIRSTCOMPARATOR.

The residue voltage V_(RES) is applied to the negative input nodethrough the third capacitor C₂₃. If the sixth switch SW_(LSB2b) isswitched off and the seventh switch SW_(LSB2) is switched on, the fineramping voltage of the ramp signal V_(RAMP) is applied to the positiveinput node of the second comparator SECOND COMPARATOR and is ramped withthe fine step.

The second comparator SECOND COMPARATOR compares the positive inputvoltage V_(IN23) to the negative input voltage V_(RES) and outputs asecond comparison result signal when the reset voltage V_(RST) ischanged to be less than the sum of the coarse ramping voltage and thefine ramping voltage (that is, changed from reset voltage-coarsevoltage-fine ramping voltage >0 to reset voltage-coarse rampingvoltage-fine ramping voltage <0, as indicated by reference numeral 440of FIG. 4C). The output voltage V_(OUT2) of the second comparator SECONDCOMPARATOR is latched, and the counted code value is stored as an LSBconversion code value on a register.

Since a full swing range of the reset voltage V_(RST) is smaller than afull swing range of a signal voltage V_(SIG), the number of coarse stepsof the reset signal V_(RST) may be confined to be less than the numberof coarse steps of the signal voltage V_(SIG). Also, for example, theoffset voltage V_(offset) may be greater than or equal to one coarsestep.

Subsequently, if the signal voltage V_(SIG) of the pixel signalV_(PIXEL) is applied, after the code value counted by each latching time(indicated by reference numerals 450 and 460 of FIG. 4C) is stored byperforming the above-described two-step operations, the digital doublesampling (DDS) may be implemented by subtracting the code value of thereset voltage V_(RST) from the code value of the signal voltage V_(SIG).

FIG. 5 is another exemplary circuit diagram illustrating the comparator42 in accordance with another embodiment of the present invention.

In the comparator 42 shown in FIG. 4A, it is difficult to acquire anabsolute voltage of a direct current (DC) bias voltage applied to thepositive input node of the second comparator. Thus, the comparator 42shown in FIG. 5 solves this problem.

Referring to FIG. 5, the comparator 42 in accordance with anotherembodiment of the present invention includes a first comparison block410 and a second comparison block 420.

The first comparison block 410 includes a first capacitor C₂₁, a firstswitch SW_(R21), a second switch SW_(S/H2), a second capacitor C₂₂, athird switch SW_(MSB2), a fourth switch SW_(RES) and a first comparatorFIRST COMPARATOR.

Since the configuration and operations of the first capacitor C₂₁, thefirst switch SW_(R21), the second switch SW_(S/H2), the second capacitorC₂₂, the third switch SW_(MSB2), the fourth switch SW_(RES) and thefirst comparator in the first comparison block 410 shown in FIG. 5 arethe same as the configuration and operations of the first capacitor C₂₁,the first switch SW_(R21), the second switch SW_(S/H2), the secondcapacitor C₂₂, the third switch SW_(MSB2), the fourth switch SW_(RES)and the first comparator FIRST COMPARATOR in the first comparison block410 shown in FIG. 4A, description of the first comparison block 410 inFIG. 5 will be omitted.

The second comparison block 420 includes a third capacitor C₂₃, a fourthcapacitor C₃₁, a fifth switch SW_(R22), a sixth switch SW_(LSB2b), aseventh switch SW_(LSB2), an eighth switch SW_(R31) and a secondcomparator SECOND COMPARATOR.

Since the configuration and operations of the third capacitor C₂₃, thefifth switch SW_(R22), the sixth switch SW_(LSB2b), the seventh switchSW_(LSB2) and a second comparator SECOND COMPARATOR in the secondcomparison block 420 shown in FIG. 5 are same as the configuration andoperations of the third capacitor C₂₃, the fifth switch SW_(R22), thesixth switch SW_(LSB2b), the seventh switch SW_(LSB2) and a secondcomparator SECOND COMPARATOR in the second comparison block 420 shown inFIG. 4A, the description of these components in the second comparisonblock 420 in FIG. 5 will be omitted.

The second comparison block 420 further comprises the fourth capacitorC₃₁ and the eighth switch SW_(R31) as compared with the secondcomparison block 420 shown in FIG. 4A.

The fourth capacitor C₃₁ is coupled between the positive input node ofthe second comparator SECOND COMPARATOR and the second terminal of theseventh switch SW_(LSB2) and transfers a changed value of the fineramping voltage.

The eighth switch SW_(R31) is coupled to form a third feedback loopbetween the output node of the second comparator and the positive inputnode of the second comparator SECOND COMPARATOR.

The absolute voltage of the DC bias voltage of the positive input nodeof the second comparator is provided as an input/output common voltageof the second comparator SECOND COMPARATOR by the eighth switchSW_(R31). The changed value of the fine ramping voltage is applied tothe positive input node of the second comparator through the fourthcapacitor C₃₁.

FIG. 6 is a diagram illustrating a CMOS image sensor including thecomparator 42 in accordance with embodiments of the present invention.

Referring to FIG. 6, the CMOS image sensor including a plurality ofcomparators 42 in accordance with embodiments of the present inventionfurther includes a pixel array 10, a row decoder 20, a ramp signalgenerator 30, a comparator assembly 40, a counter assembly 50, a memoryassembly 60, a column read-out circuit 70 and a controller 80.

The pixel array 10 outputs a pixel signal corresponding to an incidentlight.

The row decoder 20 selects and controls pixels of the pixel array row byrow.

The ramp signal generator 30 generates a ramp signal V_(RAMP), whichincludes the coarse ramping signal and the fine ramping signal, inresponse to a control signal of the controller.

The comparator assembly 40 compares the ramp signal V_(RAMP) of the rampsignal generator 40 with each pixel signal outputted from the pixelarray.

The counter assembly 50 counts a clock of the controller 80 according toan output signal of the comparator assembly 40.

The memory assembly 60 stores a counting information of the counterassembly 50 according to the control of the controller 80.

The column read-out circuit 70 outputs sequentially the stored data ofthe memory assembly 60 as a pixel data PXDATA according to the controlof the controller 80.

The controller 80 controls operations of the row decoder 20, the rampsignal generator 30, the comparator assembly 40, the counter assembly50, the memory assembly 60 and the column read-out circuit 70.

The comparator assembly 40 includes the comparator 42 shown in FIG. 4Aor the comparator 42 shown in FIG. 5 in accordance with embodiments ofthe present invention.

Thus, in embodiments of the present invention, by performing ananalog-to-digital converting operation on a residue value, which is adifference between a sampling value of a pixel signal and a samplingvalue of coarse step voltage, the linearity error caused by aconventional two-step single-slope analog-to-digital conversionstructure is prevented.

Although various embodiments have been described and illustrated, itwill be apparent to those skilled in the art that various changes andmodifications may be made without departing from the spirit and scope ofthe disclosure as defined in the following claims.

What is claimed is:
 1. A comparator, comprising: a first comparisonblock suitable for sampling a pixel signal, comparing a voltage of asampled pixel signal to a coarse ramping voltage, outputting a firstcomparison result signal, sampling a coarse step voltage and outputtinga residue voltage, representing a difference between the voltage of thesampled pixel signal and the sampled coarse step voltage; and a secondcomparison block suitable for comparing a fine ramping voltage to theresidue voltage outputted by the first comparison block and outputting asecond comparison result signal.
 2. The comparator of claim 1, whereinthe residue voltage is acquired by subtracting the sampled coarse stepvoltage from the voltage of the sampled pixel signal.
 3. The comparatorof claim 1, wherein the comparator is configured such that the number ofcoarse steps of a reset signal is less than the number of coarse stepsof a signal voltage when the pixel signal is the reset signal.
 4. Thecomparator of claim 1, wherein the first comparison block includes: afirst capacitor suitable for sampling the pixel signal; a first switchcoupled between two input nodes of a first comparator; a second switchsuitable for switching on or off the coarse ramping voltage; a secondcapacitor suitable for being coupled to the second switch and samplingthe coarse step voltage; a third switch coupled between the secondcapacitor and a ground terminal; and a fourth switch coupled to form afirst feedback loop between the second capacitor and an output node ofthe first comparator; and the first comparator suitable for comparingthe voltage of the sampled pixel signal sampled by the first capacitorto the coarse ramping voltage applied through the second switch,outputting the first comparison result signal, and outputting theresidue voltage.
 5. The comparator of claim 1, wherein the secondcomparison block includes: a third capacitor suitable for transferringthe residue voltage outputted from the first comparison block to asecond comparator; a fifth switch coupled to form a second feedback loopbetween a negative input node of the second comparator and an outputnode of the second comparator; a sixth switch coupled between a positiveinput node of the second comparator and a ground terminal; a seventhswitch suitable for switching on or off the fine ramping voltage; andthe second comparator suitable for comparing the residue voltage appliedthrough the third capacitor to the fine ramping voltage applied throughthe seventh switch and outputting the second comparison result signal.6. The comparator of claim 5, wherein the second comparison blockfurther includes: an eighth switch coupled to form a third feedback loopbetween the positive input node of the second comparator and the outputnode of the second comparator; and a fourth capacitor coupled betweenthe seventh switch and the positive input node of the second comparatorand suitable for transferring a changed value of the fine rampingvoltage to the second comparator.
 7. A complementary metal oxidesemiconductor (CMOS) image sensor, comprising: a pixel array suitablefor outputting a pixel signal corresponding to an incident light; a rowdecoder suitable for selecting and controlling pixels of the pixel arrayrow by row according to a control signal of a controller; a ramp signalgenerator suitable for generating a coarse ramping signal and a fineramping signal according to the control signal of the controller; afirst comparison block suitable for sampling the pixel signal outputtedfrom the pixel array, comparing a sampled pixel signal to the coarseramping signal outputted by the ramp signal generator, outputting afirst comparison result signal, sampling a coarse step voltage andoutputting a residue voltage, representing a difference between avoltage of the sampled pixel signal and the sampled coarse step voltage;and a second comparison block suitable for comparing the fine rampingvoltage outputted from the ramp signal generator to the residue voltageoutputted by the first comparison block and outputting a secondcomparison result signal; a counter suitable for counting a clock of thecontroller according to the first comparison result signal outputted bythe first comparison block and the second comparison result signaloutputted by the second comparison block; a memory suitable for storingcounting information of the counter according to the control signal ofthe controller; a column read-out circuit suitable for outputting datastored in the memory according to the control signal of the controller;and the controller suitable for controlling operations of the rowdecoder, the ramp signal generator, the first comparison block, thesecond comparison block, the counter, the memory, and the columnread-out circuit.
 8. The CMOS image sensor of claim 7, wherein theresidue voltage is acquired by subtracting the sampled coarse stepvoltage from the voltage of the sampled pixel signal.
 9. The CMOS imagesensor of claim 7, wherein the comparator is configured such that thenumber of coarse steps of a reset signal is less than the number ofcoarse steps of a signal voltage when the pixel signal is the resetsignal.
 10. The CMOS image sensor of claim 7, wherein the firstcomparison block includes: a first capacitor suitable for sampling thepixel signal; a first switch coupled between two input nodes of a firstcomparator; a second switch suitable for switching on or off the coarseramping voltage; a second capacitor suitable for being coupled to thesecond switch and sampling the coarse step voltage; a third switchcoupled between the second capacitor and a ground terminal; a fourthswitch coupled to form a first feedback loop between the secondcapacitor and an output node of the first comparator; and the firstcomparator suitable for comparing the sampled pixel signal of the firstcapacitor to the coarse ramping voltage applied through the secondswitch, outputting the first comparison result signal, and outputtingthe residue voltage.
 11. The CMOS image sensor of claim 7, wherein thesecond comparison block includes: a third capacitor suitable fortransferring the residue voltage outputted from the first comparisonblock to a second comparator; a fifth switch coupled to form a secondfeedback loop between a negative input node of the second comparator andan output node of the second comparator; a sixth switch coupled betweena positive input node of the second comparator and a ground terminal; aseventh switch suitable for switching on or off the fine rampingvoltage; and the second comparator suitable for comparing the residuevoltage applied through the first capacitor to the fine ramping voltageapplied through the third switch and outputting the second comparisonresult signal.
 12. The CMOS image sensor of claim 11, wherein the secondcomparison block further includes: an eighth switch coupled to form athird feedback loop between the positive input node of the secondcomparator and the output node of the second comparator; and a fourthcapacitor coupled between the seventh switch and the positive input nodeof the second comparator and suitable for transferring a changed valueof the fine ramping voltage to the second comparator.
 13. Acomplementary metal oxide semiconductor (CMOS) image sensor comprising:a pixel array suitable for generating a pixel signal; a ramp signalgenerator suitable for generating coarse and fine ramping signals; afirst comparison block suitable for generating a first comparison resultsignal by comparing the pixel signal to the coarse ramping signal; asecond comparison block suitable for generating a second comparisonresult signal by comparing the fine ramping signal to a differencebetween the pixel signal and a coarse step signal; a counter suitablefor counting a clock according to the first and second comparison resultsignals; and a column read-out circuit suitable for outputting a countresult of the counter.